Research Gallery

Trends in process variations for an Altera Cyclone II FPGA EP2C35 device. Results are from silicon measurements. Different Colors give the delay of different logic blocks in nanoseconds as a function of horizontal and vertical locations.

Layout of a simple cache memory designed using AMI 0.5 micron technology. The processor has been designed by students in EN160 Spring '08 class and tapped out to MOSIS in June 6th 2008. Total area is 1.5 mm x 1.5mm.

A TSP Tour using our Match Twice and Stitch heuristic. The resultant tour is only 4.00% above the Held-Karp lower bound.

Placement of the IBM benchmark Big Blue 4 (2.1 million gates) using APlace 2.0 (winner of the 2005 ISPD VLSI Placement contest).

Placement of a functional block from an Intel microprocessors using linear programming based placement.