Publications

Code: J for Journal, B for Book Chapter and C for Conference.

2009
C	S. Reda, A. Si and R. I. Bahar, "Reducing the Leakage and Timing Variability of 2D ICs Using 3D ICs," International Symposium on Low Power Electronics and Design, pp. 283 - 286, 2009.
C	S. Reda, "Using Circuit Structural Analysis Techniques for Networks in Systems Biology," System Level Interconnect Prediction, pp. 37 - 44, 2009.
C	R. Cochran and S. Reda, "Spectral Techniques for High-Resolution Thermal Characterization with Limited Sensor Data," Design Automation Conference, pp. 478 - 483, 2009.
C	R. Le, S. Reda and R. I. Bahar, "High-Performance, Cost-Effective Heterogeneous 3D FPGA Architectures," Great Lakes VLSI Symposium, pp. 251 - 256, 2009.
C	M. Kadin, S. Reda and G. Uht, "Central vs. Distributed Dynamic Thermal Management for Multi-Core Processors: Which one is better?," Great Lakes VLSI Symposium, pp. 137 - 140, 2009.
C	S. Reda and S. Nassif, "Analyzing the Impact of Process Variations on Parametric Measurements: Novel Models and Applications," Design, Automation, Test in Europe, pp. 375 - 380, 2009.
J	S. Reda, G. Smith and L. Smith, "Maximizing the Functional Yield of Wafer-to-Wafer 3D Integration," in IEEE Transactions on Very Large Scale Integration Systems, 17(9), pp. 1357 - 1362, 2009.
2008
J	C. Ferri, S. Reda and R. I. Bahar, "Parametric Yield Management for 3D ICs: Models and Strategies for Improvement,"ACM Journal on Emerging Technologies in Computing Systems, Special Issue on 3D ICs, 4(4), pp. 19:1 - 19:22, 2008.
C	M. Kadin and S. Reda, "Frequency and Voltage Planning for Multi-Core Processors Under Thermal Constraints," International Conference on Computer Design, pp. 463 - 470, 2008.
C	M. Kadin and S. Reda, "Frequency Planning for Multi-Core Processors Under Thermal Constraints," International Symposium on Low Power Electronics and Design, pp. 213-216, 2008.
C	B. Hargreaves, H. Hult and S. Reda, "Within-die Process Variations: How Accurately can They Be Statistically Modeled?" Proc. Asia-Pacific Design Automation Conference, 2008, pp. 524-530. Best Paper Candidate.
2007
C	C. Ferri, S. Reda and R. I. Bahar, "Strategies for Improving the Parametric Yield and Profits of 3D ICs," Proc. International Conference on Computer-Aided Design, 2007, pp. 220-226.
C	D. Meisner and S. Reda, "Hardware Libraries: An Architecture for Economic Acceleration in Soft Multi-Core Environments," Proc. International Conference on Computer Design, 2007, pp. 189-196.
C	A. B. Kahng, S. Reda and P. Sharma, " On-Line Adjustable Buffering for Runtime Power Reduction," in Proc. International Symposium on Quality Electronic Design Automation, 2007, pp. 550 - 555.
B	A. Kahng and S. Reda and Q. Wang, "APlace: A High Quality, Large-Scale Analytical Placer," Modern Circuit Placement: Best Practices and Results, Springer, 2007, J. Cong and G-J. Nam (ed.), pp. 163 - 187.
2006
B	A. Kahng, I. Mandoiu, S. Reda, A. Zelikovsky and X. Xu, "Computer-Aided Optimization of DNA Array Design and Manufacturing," Design Automation Methods and Tools for Microfluidics-Based Biochips, Springer, 2006, K. Chakrabarty (ed.), pp. 253 - 269.
J	A. B. Kahng, I. Mandoiu, S. Reda, X. Xu and A. Zelikvosky, "Computer-Aided Optimization of DNA Array Design and Manufacturing", IEEE Transactions on Computer-Aided Design, Vol. 25(2), 2006, pp. 305 - 320. [pdf]
J	A. Kahng and S. Reda, "New and Improved BIST Diagnosis Techniques from Combinatorial Group Theory," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25(3), 2006, pp. 533 - 543. [pdf]
J	A. Kahng and S. Reda, "Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, Vol. 25(12), pp. 2806 - 2819. [pdf]
J	A. Kahng and S. Reda, "Wirelength Minimization for Min-Cut Placements via Placement Feedback," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25(7), 2006, pp. 1301 - 1312. [pdf]
J	C. Alpert, A. B. Kahng, G-J. Nam, S. Reda and P. Villarubia "A Fast Hierarchical Quadratic Placement Algorithm", 2006, IEEE Transactions on Computer Aided Design, Vol. 25(4), 2006, pp. 678 - 691. [pdf]
C	Andrew B. Kahng and S. Reda, "A Tale of Two Nets: Studies of Wirelength Progression in Physical Design", System Level Interconnect Prediction Workshop, 2006, pp. 17 - 24. [pdf] [ppt]
C	S. Reda and A. Chowdhary, "Effective Linear Programming Based Placement Methods", International Symposium on Physical Design, 2006, pp. 186 - 191. [pdf] [ppt]
2005
B	A. Kahng and S. Reda, "Digital Layout - Placement," The CRC Handbook of EDA for IC Design, CRC Press, 2005, G. Martin and L. Lavagno (ed.), Vol. 2., pp. 5.1 - 5.23.
C	A. B. Kahng and S. Reda, "Intrinsic Shortest Path Length: A New, Accurate A Priori Wirelength Estimator", Intl. Conf. on Computer Aided Design, 2005, pp. 173 - 180. [ppt]
C	A. B. Kahng, S. Reda and Q. Wang "Architecture and Details of a High Quality, Large-Scale Analytical Placer", Intl. Conf. on Computer Aided Design, 2005, pp. 891 - 898. Best Paper Candidate. [ppt]
C	Y. Cheon, P-H. Ho, A. Kahng, S. Reda and Q. Wang, "Power-Aware Placement," in Design Automation Conference, 2005. pp. 795-800.
C	A. B. Kahng, S. Reda, and Q. Wang, "APlace: A General Analytic Placement Framework"; International Symposium on Physical Design, 2005, pp. 233-235. Short invited - 1st place winner of the ISPD 2005 placement contest. [ppt]
C	A. B. Kahng and S. Reda, "Evaluation of Placer Suboptimality Via Zero-Change Netlist Transformations," International Symposium on Physical Design, 2005, pp. 208-215. [ppt]
C	C. Alpert, A. B. Kahng, G-J. Nam, S. Reda and P. Villarubia, "A Semi-Persistent Clustering Technique for VLSI Circuit Placement," International Symposium on Physical Design, 2005, pp. 200-207. [ppt]
2004
C	A. B. Kahng and S. Reda, "Reticle Floorplanning With Guaranteed Yield for Multi-Projects Wafers," in International Conference on Computer Design, 2004, pp. 106-110. [ppt]
C	A. B. Kahng and S. Reda, "Placement Feedback: A Concept and Method for Better Min-Cut Placements," ACM/IEEE Design Automation Conference, 2004, pp. 357-362. [ppt]
J	A. B. Kahng and S. Reda, "Match Twice and Stitch: A New TSP Tour Construction Heuristic," Operations Research Letters, 2004, 32(6). pp. 499-509. The most downloaded "hottest" article of Operations Research Letters in the 1st quarter of 2005 (cached link).
C	A. B. Kahng, I. Markov and S. Reda, "On Legalization of Row-Based Placements" IEEE Great Lakes VLSI Symposium, 2004, pp. 214-219. [ppt]
C	A. B. Kahng, I. Markov and S. Reda, "Boosting: A Min-Cut Placement with Improved Signal Delay", Design Automation and Test in Europe, 2004, pp. 1098-1103. [ppt]
C	A. B. Kahng and S. Reda, "Combinatorial Group Testing Methods for the BIST Diagnosis Problem", Asian South-Pacific Design Automation Conference 2004, pp. 113-116.[ppt]
J	A. B. Kahng, I. Mandoiu, P. Pevzner, S. Reda, and A. Zelikvosky, "Scalable Heuristics for Design of DNA Probe Arrays", Journal of Computational Biology, Volume 11(2-3), pp. 429-447, 2004.
2003
C	A. B. Kahng, I. Mandoiu, S. Reda, X. Xu and A. Zelikvosky, " Evaluation of Placement Techniques for DNA Probe Array Layout", Intl. Conf. on Computer Aided Design, 2003, pages 262-269. [pdf][ppt]
C	A. B. Kahng, I. Mandoiu, S. Reda, X. Xu and A. Zelikvosky, " Design Flow Enhancements for DNA Arrays", Intl. Conf. on Computer Design, 2003, pages 116-123. [pdf][ppt]
C	A. B. Kahng, I. Mandoiu, P. Pevzner, S. Reda, and A. Zelikvosky, " Engineering a Scalable Placement Heuristic for DNA Probe Arrays", Intl. Conf. on Research in Computational Molecular Biology, 2003, pages 148-156. [pdf]
2002
C	A. B. Kahng, I. I. Mandoiu, P. A. Pevzner, S. Reda, and A. A. Zelikovsky, "Border Length Minimization in DNA Array Design", In Proc. 2nd Workshop on Algorithms in Bioinformatics (WABI), 2002, pages 435-438. [pdf]
C	S. Reda, R. Drechsler, A. Orailoglu, "On the Relation between BDDs and SAT for Equivalence Checking," International Symposium on Quality Electronic Design Automation, ISQED, 2002, pp. 394-399. [pdf][ppt]
C	S. Reda, A. Orailoglu, "Reducing Test Application Time through Test Data Mutation," Design Automation and Test In Europe, DATE, 2002, pp. 387-393, 2002. Best paper award. [pdf][ppt]
2001
C	S. Reda, A. Salem, "Combinational Equivalence Checking using Boolean Satisfiability and Binary Decision Diagrams," Design Automation and Test In Europe, DATE, 2001, pp. 122-126. [pdf]
C	S. Reda, A. Wahba, A. Salem, D. Borionne, M. Ghonaimy, "On the Use of Don't Cares during Reachability Analysis," International Symposium on Circuits & Systems, ISCAS, 2001, pp. 121-124 Vol(5). [pdf]
Patents
	C. Alpert, G-J. Nam, S. Reda and P. Villarubia, "A Semi-Persistent Clustering Technique for VLSI Circuit Placement," Issued US Patent, US7296252.