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Current Research Projects

 

Lab Mission Statement: Our laboratory works on advancing and scaling computing technologies with particular emphasis on physical synthesis and implementation methodologies. We currently work on the following projects.

Project 1.Thermal, POWER, performance management for integrated circuits

You have likely wished before if your laptop would not heat so much when it rests on your lap, and that your laptop or cell phone battery would last longer. Unfortunately performance, power and temperature are conflicting goals, and thus, they need to be jointly co-optimized and managed during the design and runtime operation of processors. Such management will get more critical in future computational machines, which will rely on many-core processors for their number crunching. Many-core machines will have numerous degrees of freedom that can control their physical behavior, and it will not be possible to scale and leverage their full potential unless these degrees of freedom are carefully managed.

 

At SCALE lab, we work on devising many innovative techniques towards an effective management of temperature, power, and performance of many-core processors. We work on methods that enable management techniques to go beyond the limitations imposed by on-die thermal sensors by accurately predicting the locations of hot spots during runtime. We also work on optimal frequency and voltage planning techniques that optimally set the frequencies and voltages of individual cores to maximize performance, limit temperature and power. In the process of working on our techniques, we follow rigorous scientific methods that lead to fundamental new understandings of the physical limits of processor management system. For our experimental verifications, we use state-of-the-art equipment, including power meters, and infra-cameras that are capable of monitoring the temporal and spatial temperatures of silicon die to a resolution of 5 microns. For example, the figure above captured using our infrared camera illustrates the thermal variations that exist on a die of a popular processor; these variations reach up to 25 Celsius degress. Please check our publications and infrastructure pages for more information.

PROJECT 2. Characterization andMODELING of process variations in NANO-SCALE SEMICONDUCTOR CIRCUITS

If you have recently purchased a computer, the large number of “flavors” available for the processor has probably bewildered you. Each one of these flavors gives a different price/performance trade-off. You probably wondered: why won’t chip manufactures make all their chips fast. Unfortunately, they can’t! In recent years advanced nanometer fabrication technologies became prone to inherent statistical variations during fabrication. Thus, two chips that follow the same identical design recipe could end up with completely different speeds after fabrication. For example, the figure above shows the speed of circuits as a function of their locations in a wafer. In response to this problem, chip manufacturers test their chips after fabrication and sell the fastest one for more money.

 

At SCALE lab, we have been working on new techniques for accurate nanometer variability characterization and modeling techniques. We have devised and implemented our own variability sensitive test structures, and we have produced rigorous statistical techniques to model these results. We also work with our industry partners to analyze the variability data emerging from their fabrication facilities. We also work on analyzing variability trends and mitigating their impacts in 3D integration technology in synergies with Project 3. Please check our publications and infrastructure pages for more information.

PROJECT 3. Yield management and Cost-effective design techniques for 3D integrated circuits

 

Moore’s law has been driving the pace of integrated semiconductor technology for the past 4 decades. While Moore’s law was incorrectly predicted to demise numerous times in the past, it certainly faces insurmountable physical limits in the next decade. Even if these physical limits are mitigated, it is unlikely that such mitigation can be achieved through economically feasible means. To avoid these limitations, 3D integration has been advocated as a means to increase the scalability of semiconductor integration beyond lithographic shrinking.

 

At SCALE lab, we work on solving some of the fundamental challenges of 3D technology. In particular yield and cost have been big challenges to overcome. Yield controls the cost of fabrication, and it can take a big hit in 3D chips as a faulty die in a 3D stack can lead to the entire demise of the 3D chip. Thus, we work on developing modeling and integration strategy techniques that allow designers and process engineers to model the impact of integrating multiple die together, and then use these models to drive the integration process to improve the fabrication yield. 3D integration also suffers from increased power densities and temperatures, and thus it is necessary to deploy effective thermal management techniques to address this challenge. Our solutions to this challenge are synergetic with our goals of Project 1. Please check our publications and infrastructure pages for more information.

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Earlier research Projects

  • Placement and routing techniques for application specific integrated circuits

  • Design automation techniques for DNA arrays (gene chips)

  • Test and verification of integrated circuits